Conventional scaled metal-oxide-semiconductor (MOS) technology has been designed for the implementation of complex large scale integrated circuits containing both analog and digital functional elements. These circuits are generally capable of moderately high speed operation. Operation in the range of gigabits per second is impaired for these circuits because of parasitic capacitances which arise as a result of the fabrication process.
An important parasitic capacitance, in this regard, is the capacitance caused by the gate overlap over the source and the drain regions in the substrate. This overlap is illustrated in FIG. 6 of a technical article by H. Fu et al., Hewlett-Packard Journal, pp. 21-7 (1982). Typically, the overlap capacitance is on the order of 0.5 fF/.mu.m.
Another important parasitic capacitance which limits operating speeds for these MOS circuits is the junction capacitance between the regions of different conductivity, i.e., between source (drain) and substrate and between source (drain) and channel.